1. Technical Field
The disclosed embodiments relate to self-timing circuits that generate internal memory control signals in semiconductor memory devices.
2. Background Information
One conventional type of semiconductor memory device is a static random access memory (SRAM) that involves an array of bit cells organized in rows and columns. Each row of bit cells has an associated word line. Each column of bit cells has an associated pair of bit lines. Each pair of bit lines is coupled to a sense amplifier. If the sense amplifier detects a positive differential voltage between its pair of bit lines, then the sense amplifier outputs a first digital logic value. If, on the other hand, the sense amplifier detects a negative differential voltage between the pair of bit lines, then the sense amplifier outputs a second digital logic value opposite the first digital logic value.
In a read operation, an address is placed on address input leads of the memory and a read/write signal is setup on a R/W input lead to indicate a read operation. Upon an edge of a clock signal, the address is latched into an address latch. Bit line precharge is disabled. The address is decoded such that a word line enable signal is supplied onto one of the word lines indicated by the address. The bit cells of the row then output their respective data values. Each bit cell causes the voltage between its associated pair of bit lines to have either a positive voltage or a negative voltage. It takes time for a bit cell to discharge or charge the capacitance of its bit lines such that the positive or negative voltage is of sufficient magnitude to be properly read by the sense amplifier. Once an adequate amount of time has passed, then a sense amplifier enable signal is supplied to the sense amplifiers. The sense amplifier enable signals cause the sense amplifiers to sense the differential voltages on the bit lines and to output the corresponding digital data values for the addressed row from the memory. If the time between the edge of the clock signal and the sense amplifier enable signal is too short, then the magnitude of the differential voltages may be too small and the sense amplifiers may output erroneous data. On the other hand, if the time between the edge of the clock signal and the sense amplifier enable signal is longer than necessary, then the access time of the memory is lengthened unnecessarily. The amount of time required for the accessed bit cells to drive the bit lines to adequate differential voltages is not constant, but rather varies with memory size, process, voltage and/or temperature.
In this type of SRAM, a circuit sometimes referred to as “self-timing circuit” generates the sense amplifier enable signal and other control signals such that the sense amplifiers are not enabled too early or unnecessarily late. The self-timing circuit uses the delay of a signal propagation path to time the assertion of the sense amplifier enable signal. The signal propagation path is made to mimic the signal propagation paths through the real memory array from the edge of the clock signal until the addressed bit cells have driven adequate differential voltages onto their respective pairs of bit lines in the real memory array. If the signal propagation path in the self-timing circuit is like the signal propagation paths in the real memory, then as the process, voltage and/or temperature (PVT) changes and affects the signal propagation paths through the real memory array, the signal propagation path in the self-timing circuit will be affected in the same way. If, for example, process, voltage and/or temperature changes reduce the rate at which bit cells in the real memory array can drive their corresponding bit lines to appropriate voltage levels, then the same process, voltage and/or temperature changes will slow the signal propagation path in the self-timing circuit resulting in an appropriately delayed assertion of the sense amplifier enable signal.
One self-timing circuit technique uses a dummy word line, a column of dummy bit cells and one or two dummy bit lines to model corresponding signal paths in the real memory array. The dummy bit cells are made to have identical layouts to the bit cells in the real memory array, and the resistances and capacitances of the dummy word line and dummy bits lines are made to be the same as the resistances and capacitances of the real word lines and real bit lines in the real memory array so that the effects of process, voltage and temperature on the signal propagation paths in the self-timing circuit and in the real memory array will track one another closely. Another self-timing circuit technique does not employ word line, bits cells and bit lines of the same layout as in the real memory array to mimic the signal propagation path in the real memory array, but rather employs high threshold voltage N-channel pull down field effect transistors (FETs) to pull-down on a timing node in the self-timing circuit. The signal propagation delay through the self-timing circuit is made to match the signal propagation delay through the real memory array by changing the number of these pull down transistors that are made conductive and are pulling down on the timing node.
Once the sense amplifiers have been enabled and have output correct digital logic values, the output data can be latched. Once the output data is latched, the sense amplifiers can be disabled to reduce power consumption of the memory. If, however, the address latch were made transparent for the next memory cycle too early with respect to disabling of the sense amplifiers, then the sense amplifiers may erroneously change the values they are outputting at the end of the prior memory read operation. To prevent this, a conventional self-timing circuit may involve gating circuitry for extending the duration of the address latch enable signal. In one example, an inverted version of the unextended address latch enable signal is supplied onto one input lead of a NAND gate. The inverted unextended address latch enable signal is delayed by passing it through a chain of an even number of inverters. The delayed signal is supplied onto a second input lead of the NAND gate. The NAND gate outputs the extended address latch enable signal that is used to control the address latch. The delay introduced by the chain of inverters serves to extend the amount of time that the address latch enable signal is a digital logic high value.